![](http://datasheet.mmic.net.cn/200000/MT41J128M16HA-107-D_datasheet_15084792/MT41J128M16HA-107-D_54.png)
Table 29: Allowed Time Before Ringback (tDVAC) for CK - CK# and DQS -
DQS# (Continued)
Slew Rate (V/ns)
tDVAC (ps) at |VIH,diff(AC) to VIL,diff(AC)|
350mV
300mV
1.4
22
159
1.2
13
155
1.0
0
150
<1.0
0
150
Note: 1. Below VIL(AC)
Slew Rate Definitions for Single-Ended Input Signals
Setup (tIS and tDS) nominal slew rate for a rising signal is defined as the slew rate be-
tween the last crossing of VREF and the first crossing of VIH(AC)min. Setup (tIS and tDS)
nominal slew rate for a falling signal is defined as the slew rate between the last crossing
of VREF and the first crossing of VIL(AC)max.
Hold (tIH and tDH) nominal slew rate for a rising signal is defined as the slew rate be-
tween the last crossing of VIL(DC)max and the first crossing of VREF. Hold (tIH and tDH)
nominal slew rate for a falling signal is defined as the slew rate between the last crossing
Table 30: Single-Ended Input Slew Rate Definition
Input Slew Rates
(Linear Signals)
Measured
Calculation
Input
Edge
From
To
Setup
Rising
VREF
VIH(AC)min
VIH(AC)min - VREF
Δ
TRS
Falling
VREF
VIL(AC)max
VREF - VIL(AC)max
Δ
TFS
Hold
Rising
VIL(DC)max
VREF
VREF - VIL(DC)max
Δ
TFH
Falling
VIH(DC)min
VREF
VIH(DC)min - VREF
Δ
TRSH
2Gb: x4, x8, x16 DDR3 SDRAM
Electrical Specifications – DC and AC
PDF: 09005aef826aaadc
2Gb_DDR3_SDRAM.pdf – Rev. K 04/10 EN
54
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