Table 19: IDD7 Measurement Loop
CK,
CK#
CKE
Sub-loop
Cycle
Number
Command
CS#
RAS#
CAS#
WE#
ODT
BA[2:0]
A[15:11]
A[10]
A[9:7]
A[6:3]
A[2:0]
Data
Toggling
Static
HIGH
0
ACT
0
1
0
–
1
RDA
0
1
0
1
0
1
0
00000000
2
D
1
0
–
3
Repeat cycle 2 until nRRD - 1
1
nRRD
ACT
0
1
0
1
0
F
0
–
nRRD + 1
RDA
0
1
0
1
0
1
0
1
0
F
0
00110011
nRRD + 2
D
1
0
1
0
F
0
–
nRRD + 3
Repeat cycle nRRD + 2 until 2 × nRRD - 1
2
2 × nRRD
Repeat sub-loop 0, use BA[2:0] = 2
3
3 × nRRD
Repeat sub-loop 1, use BA[2:0] = 3
4
4 × nRRD
D
1
0
3
0
F
0
–
4 × nRRD + 1
Repeat cycle 4 × nRRD until nFAW - 1, if needed
5
nFAW
Repeat sub-loop 0, use BA[2:0] = 4
6
nFAW + nRRD
Repeat sub-loop 1, use BA[2:0] = 5
7
nFAW + 2 × nRRD
Repeat sub-loop 0, use BA[2:0] = 6
8
nFAW + 3 × nRRD
Repeat sub-loop 1, use BA[2:0] = 7
9
nFAW + 4 × nRRD
D
1
0
7
0
F
0
–
nFAW + 4 × nRRD + 1
Repeat cycle nFAW + 4 × nRRD until 2 × nFAW - 1, if needed
10
2 × nFAW
ACT
0
1
0
F
0
–
2 × nFAW + 1
RDA
0
1
0
1
0
1
0
F
0
00110011
2 × nFAW + 2
D
1
0
F
0
–
2 × nFAW + 3
Repeat cycle 2 × nFAW + 2 until 2 × nFAW + nRRD - 1
11
2 × nFAW + nRRD
ACT
0
1
0
1
0
–
2 × nFAW + nRRD + 1
RDA
0
1
0
1
0
1
0
1
0
00000000
2 × nFAW + nRRD + 2
D
1
0
1
0
–
2 × nFAW + nRRD + 3
Repeat cycle 2 × nFAW + nRRD + 2 until 2 × nFAW + 2 × nRRD - 1
12
2 × nFAW + 2 × nRRD
Repeat sub-loop 10, use BA[2:0] = 2
13
2 × nFAW + 3 × nRRD
Repeat sub-loop 11, use BA[2:0] = 3
14
2 × nFAW + 4 × nRRD
D
1
0
3
0
–
2 × nFAW + 4 × nRRD + 1
Repeat cycle 2 × nFAW + 4 × nRRD until 3 × nFAW - 1, if needed
15
3 × nFAW
Repeat sub-loop 10, use BA[2:0] = 4
2Gb: x4, x8, x16 DDR3 SDRAM
Electrical Specifications – IDD Specifications and Conditions
Definitions
PDF: 09005aef826aaadc
2Gb_DDR3_SDRAM.pdf – Rev. K 04/10 EN
41
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