![](http://datasheet.mmic.net.cn/200000/MT41J128M16HA-107-D_datasheet_15084792/MT41J128M16HA-107-D_74.png)
Speed Bin Tables
Table 52: DDR3-1066 Speed Bins
DDR3-1066 Speed Bin
-187E
-187
Units
Notes
CL-tRCD-tRP
7-7-7
8-8-8
Parameter
Symbol
Min
Max
Min
Max
ACTIVATE to internal READ or WRITE
delay time
tRCD
13.125
–
15
–
ns
PRECHARGE command period
tRP
13.125
–
15
–
ns
ACTIVATE-to-ACTIVATE or REFRESH
command period
tRC
50.625
–
52.5
–
ns
ACTIVATE-to-PRECHARGE command
period
tRAS
37.5
9 x tREFI
37.5
9 x tREFI
ns
CL = 5
CWL = 5
tCK (AVG)
3.0
3.3
3.0
3.3
ns
CWL = 6
tCK (AVG)
Reserved
ns
CL = 6
CWL = 5
tCK (AVG)
2.5
3.3
2.5
3.3
ns
CWL = 6
tCK (AVG)
Reserved
ns
CL = 7
CWL = 5
tCK (AVG)
Reserved
ns
CWL = 6
tCK (AVG)
1.875
<2.5
Reserved
ns
CL = 8
CWL = 5
tCK (AVG)
Reserved
ns
CWL = 6
tCK (AVG)
1.875
<2.5
1.875
<2.5
ns
Supported CL settings
5, 6, 7, 8
5, 6, 8
CK
Supported CWL settings
5, 6
CK
Notes: 1. tREFI depends on TOPER.
2. The CL and CWL settings result in tCK requirements. When making a selection of tCK,
both CL and CWL requirement settings need to be fulfilled.
3. Reserved settings are not allowed.
2Gb: x4, x8, x16 DDR3 SDRAM
Speed Bin Tables
PDF: 09005aef826aaadc
2Gb_DDR3_SDRAM.pdf – Rev. K 04/10 EN
74
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