![](http://datasheet.mmic.net.cn/200000/MT41J128M16HA-107-D_datasheet_15084792/MT41J128M16HA-107-D_143.png)
SRT vs. ASR
If the normal case temperature limit of 85°C is not exceeded, then neither SRT nor ASR
is required, and both can be disabled throughout operation. However, if the extended
temperature option of +95°C is needed, the user is required to provide a 2X refresh rate
during (manual) refresh and to enable either the SRT or the ASR to ensure self refresh is
performed at the 2X rate.
SRT forces the DRAM to switch the internal self refresh rate from 1X to 2X. Self refresh is
performed at the 2X refresh rate regardless of the case temperature.
ASR automatically switches the DRAM’s internal self refresh rate from 1X to 2X. Howev-
er, while in self refresh mode, ASR enables the refresh rate to automatically adjust
between 1X to 2X over the supported temperature range. One other disadvantage with
ASR is the DRAM cannot always switch from a 1X to a 2X refresh rate at an exact case
temperature of +85°C. Although the DRAM will support data integrity when it switches
from a 1X to a 2X refresh rate, it may switch at a lower temperature than +85°C.
Since only one mode is neccesary, SRT and ASR cannot be enabled at the same time.
DYNAMIC ODT
The dynamic ODT (RTT(WR)) feature is defined by MR2[10, 9]. Dynamic ODT is enabled
when a value is selected. This new DDR3 SDRAM feature enables the ODT termination
value to change without issuing an MRS command, essentially changing the ODT termi-
nation on-the-fly.
With dynamic ODT (RTT(WR)) enabled, the DRAM switches from normal ODT (RTT,nom)
to dynamic ODT (RTT(WR)) when beginning a WRITE burst and subsequently switches
back to ODT (RTT,nom) at the completion of the WRITE burst. If RTT,nom is disabled, the
RTT,nom value will be High-Z. Special timing parameters must be adhered to when dy-
namic ODT (RTT(WR)) is enabled: ODTLcnw, ODTLcnw4, ODTLcnw8, ODTH4, ODTH8,
and tADC.
Dynamic ODT is only applicable during WRITE cycles. If ODT (RTT,nom) is disabled, dy-
namic ODT (RTT(WR)) is still permitted. RTT,nom and RTT(WR) can be used independent of
one other. Dynamic ODT is not available during write leveling mode, regardless of the
state of ODT (RTT,nom). For details on dynamic ODT operation, refer to On-Die Termina- 2Gb: x4, x8, x16 DDR3 SDRAM
Mode Register 2 (MR2)
PDF: 09005aef826aaadc
2Gb_DDR3_SDRAM.pdf – Rev. K 04/10 EN
143
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