![](http://datasheet.mmic.net.cn/200000/MT41J128M16HA-107-D_datasheet_15084792/MT41J128M16HA-107-D_192.png)
Table 85: Mode Registers for RTT,nom
MR1 (RTT,nom)
RTT,nom (RZQ)
RTT,nom (Ohms)
RTT,nom Mode Restriction
M9
M6
M2
0
Off
n/a
0
1
RZQ/4
60
Self refresh
0
1
0
RZQ/2
120
0
1
RZQ/6
40
1
0
RZQ/12
20
Self refresh, write
1
0
1
RZQ/8
30
1
0
Reserved
n/a
1
Reserved
n/a
Note: 1. RZQ
= 240Ω. If RTT,nom is used during WRITEs, only RZQ/2, RZQ/4, RZQ/6 are allowed.
Table 86: Mode Registers for RTT(WR)
MR2 (RTT(WR))
RTT(WR) (RZQ)
RTT(WR) (Ohms)
M10
M9
0
Dynamic ODT off: WRITE does not affect RTT,nom
0
1
RZQ/4
60
1
0
RZQ/2
120
1
Reserved
Table 87: Timing Diagrams for Dynamic ODT
Figure and Page
Title
Dynamic ODT: ODT Asserted Before and After the WRITE, BC4
Dynamic ODT: Without WRITE Command
Dynamic ODT: ODT Pin Asserted Together with WRITE Command for 6 Clock Cycles, BL8
Dynamic ODT: ODT Pin Asserted with WRITE Command for 6 Clock Cycles, BC4
Dynamic ODT: ODT Pin Asserted with WRITE Command for 4 Clock Cycles, BC4
2Gb: x4, x8, x16 DDR3 SDRAM
Dynamic ODT
PDF: 09005aef826aaadc
2Gb_DDR3_SDRAM.pdf – Rev. K 04/10 EN
192
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