Write Leveling Procedure
A memory controller initiates the DRAM write leveling mode by setting MR1[7] to a 1,
assuming the other programable features (MR0, MR1, MR2, and MR3) are first set and
the DLL is fully reset and locked. The DQ balls enter the write leveling mode going from
a High-Z state to an undefined driving state, so the DQ bus should not be driven. Dur-
ing write leveling mode, only the NOP or DES commands are allowed. The memory
controller should attempt to level only one rank at a time; thus, the outputs of other
ranks should be disabled by setting MR1[12] to a 1 in the other ranks. The memory con-
troller may assert ODT after a tMOD delay as the DRAM will be ready to process the
ODT transition. ODT should be turned on prior to DQS being driven LOW by at least
ODTL on delay (WL - 2 tCK), provided it does not violate the aforementioned tMOD de-
lay requirement.
The memory controller may drive DQS LOW and DQS# HIGH after tWLDQSEN has
been satisfied. The controller may begin to toggle DQS after tWLMRD (one DQS toggle
is DQS transitioning from a LOW state to a HIGH state with DQS# transitioning from a
HIGH state to a LOW state, then both transition back to their original states). At a mini-
mum, ODTL on and tAON must be satisfied at least one clock prior to DQS toggling.
After tWLMRD and a DQS LOW preamble (tWPRE) have been satisfied, the memory con-
troller may provide either a single DQS toggle or multiple DQS toggles to sample CK for
a given DQS-to-CK skew. Each DQS toggle must not violate tDQSL (MIN) and tDQSH
(MIN) specifications. tDQSL (MAX) and tDQSH (MAX) specifications are not applicable
during write leveling mode. The DQS must be able to distinguish the CK’s rising edge
within tWLS and tWLH. The prime DQ will output the CK’s status asynchronously from
the associated DQS rising edge CK capture within tWLO. The remaining DQ that always
drive LOW when DQS is toggling must be LOW within tWLOE after the first tWLO is sat-
isfied (the prime DQ going LOW). As previously noted, DQS is an input and not an
for the overall write leveling procedure.
The memory controller will likely sample each applicable prime DQ state and deter-
mine whether to increment or decrement its DQS delay setting. After the memory
controller performs enough DQS toggles to detect the CK’s 0-to-1 transition, the memo-
ry controller should lock the DQS delay setting for that DRAM. After locking the DQS
setting, leveling for the rank will have been achieved, and the write leveling mode for
the rank should be disabled or reprogrammed (if write leveling of another rank follows).
2Gb: x4, x8, x16 DDR3 SDRAM
Write Leveling
PDF: 09005aef826aaadc
2Gb_DDR3_SDRAM.pdf – Rev. K 04/10 EN
127
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