On-Die Termination (ODT)
ODT is a feature that enables the DRAM to enable/disable and turn on/off termination
resistance for each DQ, DQS, DQS#, and DM for the x4 and x8 configurations (and
TDQS, TDQS# for the x8 configuration, when enabled). ODT is applied to each DQ,
UDQS, UDQS#, LDQS, LDQS#, UDM, and LDM signal for the x16 configuration.
The ODT feature is designed to improve signal integrity of the memory channel by ena-
bling the DRAM controller to independently turn on/off the DRAM’s internal termina-
tion resistance for any grouping of DRAM devices. The ODT feature is not supported
during DLL disable mode (simple functional representation shown below). The switch
is enabled by the internal ODT control logic, which uses the external ODT ball and oth-
er control information.
Figure 108: On-Die Termination
ODT
VDDQ/2
RTT
Switch
DQ, DQS, DQS#,
DM, TDQS, TDQS#
To other
circuitry
such as
RCV,
. . .
Functional Representation of ODT
The value of RTT (ODT termination value) is determined by the settings of several mode
mode (must be turned off prior to self refresh entry) or if mode registers MR1 and MR2
are programmed to disable ODT. ODT is comprised of nominal ODT and dynamic ODT
modes and either of these can function in synchronous or asynchronous mode (when
the DLL is off during precharge power-down or when the DLL is synchronizing). Nomi-
nal ODT is the base termination and is used in any allowable ODT state. Dynamic ODT
is applied only during writes and provides OTF switching from no RTT or RTT,nom to
RTT(WR).
The actual effective termination, RTT(EFF), may be different from the RTT targeted due to
nonlinearity of the termination. For RTT(EFF) values and calculations, see ODT Character- Nominal ODT
ODT (NOM) is the base termination resistance for each applicable ball, it is enabled or
disabled via MR1[9, 6, 2] (see Mode Register 1 (MR1) Definition), and it is turned on or
off via the ODT ball.
2Gb: x4, x8, x16 DDR3 SDRAM
On-Die Termination (ODT)
PDF: 09005aef826aaadc
2Gb_DDR3_SDRAM.pdf – Rev. K 04/10 EN
189
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