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| 型号： | MT41J128M16HA-107:D |
| 元件分类： | DRAM |
| 英文描述： | 128M X 16 DDR DRAM, PBGA96 |
| 封装： | 9 X 14 MM, LEAD FREE, FBGA-96 |
| 文件页数： | 189/210页 |
| 文件大小： | 12448K |
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List of Figures
Figure 1: DDR3 Part Numbers ......................................................................................................................... 2
Figure 2: Simplified State Diagram ................................................................................................................. 11
Figure 3: 512 Meg x 4 Functional Block Diagram ............................................................................................. 14
Figure 4: 256 Meg x 8 Functional Block Diagram ............................................................................................. 15
Figure 5: 128 Meg x 16 Functional Block Diagram ........................................................................................... 15
Figure 6: 78-Ball FBGA – x4, x8 (Top View) ...................................................................................................... 16
Figure 7: 82-Ball FBGA – x4, x8 (Top View) ...................................................................................................... 17
Figure 8: 96-Ball FBGA – x16 (Top View) ......................................................................................................... 18
Figure 9: 78-Ball FBGA – x4, x8; "DA" ............................................................................................................. 25
Figure 10: 78-Ball FBGA – x4, x8; "HX" ............................................................................................................ 26
Figure 11: 82-Ball FBGA – x4, x8; "JE" ............................................................................................................. 27
Figure 12: 96-Ball FBGA – x16; "HA" ............................................................................................................... 28
Figure 13: Thermal Measurement Point ......................................................................................................... 31
Figure 14: Input Signal .................................................................................................................................. 50
Figure 15: Overshoot ..................................................................................................................................... 51
Figure 16: Undershoot .................................................................................................................................. 51
Figure 17: VIX for Differential Signals .............................................................................................................. 52
Figure 18: Single-Ended Requirements for Differential Signals ........................................................................ 53
Figure 19: Definition of Differential AC-Swing and tDVAC ............................................................................... 53
Figure 20: Nominal Slew Rate Definition for Single-Ended Input Signals ......................................................... 55
Figure 21: Nominal Differential Input Slew Rate Definition for DQS, DQS# and CK, CK# .................................. 56
Figure 22: ODT Levels and I-V Characteristics ................................................................................................ 57
Figure 23: ODT Timing Reference Load .......................................................................................................... 60
Figure 24: tAON and tAOF Definitions ............................................................................................................ 61
Figure 25: tAONPD and tAOFPD Definitions ................................................................................................... 61
Figure 26: tADC Definition ............................................................................................................................. 62
Figure 27: Output Driver ............................................................................................................................... 63
Figure 28: DQ Output Signal .......................................................................................................................... 70
Figure 29: Differential Output Signal .............................................................................................................. 71
Figure 30: Reference Output Load for AC Timing and Output Slew Rate .......................................................... 71
Figure 31: Nominal Slew Rate Definition for Single-Ended Output Signals ....................................................... 72
Figure 32: Nominal Differential Output Slew Rate Definition for DQS, DQS# ................................................... 73
Figure 33: Nominal Slew Rate and tVAC for tIS (Command and Address – Clock) ............................................. 101
Figure 34: Nominal Slew Rate for tIH (Command and Address – Clock) .......................................................... 102
Figure 35: Tangent Line for tIS (Command and Address – Clock) .................................................................... 103
Figure 36: Tangent Line for tIH (Command and Address – Clock) ................................................................... 104
Figure 37: Nominal Slew Rate and tVAC for tDS (DQ – Strobe) ........................................................................ 108
Figure 38: Nominal Slew Rate for tDH (DQ – Strobe) ...................................................................................... 109
Figure 39: Tangent Line for tDS (DQ – Strobe) ............................................................................................... 110
Figure 40: Tangent Line for tDH (DQ – Strobe) ............................................................................................... 111
Figure 41: Refresh Mode ............................................................................................................................... 118
Figure 42: DLL Enable Mode to DLL Disable Mode ........................................................................................ 120
Figure 43: DLL Disable Mode to DLL Enable Mode ........................................................................................ 121
Figure 44: DLL Disable tDQSCK Timing ........................................................................................................ 122
Figure 45: Change Frequency During Precharge Power-Down ....................................................................... 124
Figure 46: Write Leveling Concept ................................................................................................................ 125
Figure 47: Write Leveling Sequence ............................................................................................................... 128
Figure 48: Exit Write Leveling ....................................................................................................................... 129
Figure 49: Initialization Sequence ................................................................................................................. 131
Figure 50: MRS to MRS Command Timing (tMRD) ......................................................................................... 132
2Gb: x4, x8, x16 DDR3 SDRAM
PDF: 09005aef826aaadc
2Gb_DDR3_SDRAM.pdf – Rev. K 04/10 EN
8
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2006 Micron Technology, Inc. All rights reserved.
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