ZQ CALIBRATION Operation
The ZQ CALIBRATION command is used to calibrate the DRAM output drivers (RON)
and ODT values (RTT) over process, voltage, and temperature, provided a dedicated
240Ω (±1%) external resistor is connected from the DRAM’s ZQ ball to VSSQ.
DDR3 SDRAM need a longer time to calibrate RON and ODT at power-up initialization
and self refresh exit and a relatively shorter time to perform periodic calibrations. DDR3
SDRAM defines two ZQ CALIBRATION commands: ZQCL and ZQCS. An example of ZQ
calibration timing is shown below.
All banks must be precharged and tRP must be met before ZQCL or ZQCS commands
can be issued to the DRAM. No other activities (other than another ZQCL or ZQCS com-
mand may be issued to another DRAM) can be performed on the DRAM channel by the
controller for the duration of tZQinit or tZQoper. The quiet time on the DRAM channel
helps accurately calibrate RON and ODT. After DRAM calibration is achieved, the DRAM
should disable the ZQ ball’s current consumption path to reduce power.
ZQ CALIBRATION commands can be issued in parallel to DLL RESET and locking time.
Upon self refresh exit, an explicit ZQCL is required if ZQ calibration is desired.
In dual-rank systems that share the ZQ resistor between devices, the controller must
not allow overlap of tZQinit, tZQoper, or tZQcs between ranks.
Figure 64: ZQ Calibration Timing (ZQCL and ZQCS)
NOP
ZQCL
NOP
Valid
ZQCS
NOP
Valid
Command
Indicates A Break in
Time Scale
T0
T1
Ta0
Ta1
Ta2
Ta3
Tb0
Tb1
Tc0
Tc1
Tc2
Address
Valid
A10
Valid
CK
CK#
Don’t Care
DQ
High-Z
3
Activities
Activ-
ities
Valid
ODT
2
Valid
1
CKE
1
Valid
tZQCS
tZQinit or tZQoper
Notes: 1. CKE must be continuously registered HIGH during the calibration procedure.
2. ODT must be disabled via the ODT signal or the MRS during the calibration procedure.
3. All devices connected to the DQ bus should be High-Z during calibration.
2Gb: x4, x8, x16 DDR3 SDRAM
ZQ CALIBRATION Operation
PDF: 09005aef826aaadc
2Gb_DDR3_SDRAM.pdf – Rev. K 04/10 EN
152
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