![](http://datasheet.mmic.net.cn/200000/MT41J128M16HA-107-D_datasheet_15084792/MT41J128M16HA-107-D_91.png)
Table 57: Electrical Characteristics and AC Operating Conditions for Speed Extensions (Continued)
Notes 1–8 apply to the entire table
Parameter
Symbol
DDR3-1866
Units
Notes
Min
Max
Begin power supply ramp to power supplies
stable
tVddpr
MIN = n/a; MAX = 200
ms
RESET# LOW to power supplies stable
tRPS
MIN = 0; MAX = 200
ms
RESET# LOW to I/O and RTT High-Z
tIOz
MIN = n/a; MAX = 20
ns
Refresh Timing
REFRESH-to-ACTIVATE or REFRESH
command period
tRFC – 1Gb
MIN = 110; MAX = 70,200
ns
tRFC – 2Gb
MIN = 160; MAX = 70,200
ns
tRFC – 4Gb
MIN = 300; MAX = 70,200
ns
Maximum refresh
period
TC ≤ +85°C
–
64 (1X)
ms
TC > +85°C
32 (2X)
ms
Maximum average
periodic refresh
TC ≤ +85°C
tREFI
7.8 (64ms/8192)
s
TC > +85°C
3.9 (32ms/8192)
s
Self Refresh Timing
Exit self refresh to commands not requiring a
locked DLL
tXS
MIN = greater of 5CK or
tRFC + 10ns; MAX = n/a
CK
Exit self refresh to commands requiring a locked DLL
tXSDLL
MIN = tDLLK (MIN); MAX = n/
a
CK
Minimum CKE low pulse width for self refresh entry to self refresh exit
timing
tCKESR
MIN = tCKE (MIN) + CK;
MAX = n/a
CK
Valid clocks after self refresh entry or power-down entry
tCKSRE
MIN = greater of 5CK or
10ns; MAX = n/a
CK
Valid clocks before self refresh exit,
power-down exit, or reset exit
tCKSRX
MIN = greater of 5CK or
10ns; MAX = n/a
CK
Power-Down Timing
CKE MIN pulse width
tCKE (MIN)
Greater of 3CK or 5ns
CK
Command pass disable delay
tCPDED
MIN = 2;
MAX = n/a
CK
Power-down entry to power-down exit timing
tPD
MIN = tCKE (MIN); MAX =
60ms
CK
Begin power-down period prior to CKE
registered HIGH
tANPD
WL - 1CK
CK
2Gb:
x4,
x8,
x16
DDR3
SDRAM
Electrical
Characteristics
and
AC
Operating
Conditions
PDF:
09005aef826aaadc
2Gb_DDR3_SDRAM.pdf
–
Rev.
K
04/10
EN
91
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Technology,
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2006
Micron
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