![](http://datasheet.mmic.net.cn/200000/MT41J128M16HA-107-D_datasheet_15084792/MT41J128M16HA-107-D_205.png)
Asynchronous to Synchronous ODT Mode Transition (Power-Down Exit)
The DRAM’s ODT may exhibit either asynchronous or synchronous behavior during
power-down exit (PDX). This transition period occurs if the DLL is selected to be off
when in precharge power-down mode by setting MR0[12] to 0. Power-down exit begins
tANPD prior to CKE first being registered HIGH, and it ends tXPDLL after CKE is first
registered HIGH. tANPD is equal to the greater of ODTL off + 1tCK or ODTL on + 1tCK.
The transition period is tANPD plus tXPDLL.
ODT assertion during power-down exit results in an RTT change as early as the lesser of
tAONPD (MIN) and ODTL on × tCK + tAON (MIN) or as late as the greater of tAONPD
(MAX) and ODTL on × tCK + tAON (MAX). ODT deassertion during power-down exit
may result in an RTT change as early as the lesser of tAOFPD (MIN) and ODTL off × tCK +
tAOF (MIN) or as late as the greater of tAOFPD (MAX) and ODTL off × tCK + tAOF (MAX).
If the AL has a large value, the uncertainty of the RTT state becomes quite large. This is
because ODTL on and ODTL off are derived from the WL, and WL is equal to CWL + AL.
ODT C: asynchronous behavior before tANPD
ODT B: ODT state changes during the transition period, with tAOFPD (MIN) less than
ODTL off × tCK + tAOF (MIN) and ODTL off × tCK + tAOF (MAX) greater than tAOFPD
(MAX)
ODT A: ODT state changes after the transition period with synchronous response
2Gb: x4, x8, x16 DDR3 SDRAM
Asynchronous to Synchronous ODT Mode Transition (Power-
Down Exit)
PDF: 09005aef826aaadc
2Gb_DDR3_SDRAM.pdf – Rev. K 04/10 EN
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