![](http://datasheet.mmic.net.cn/200000/MT41J128M16HA-107-D_datasheet_15084792/MT41J128M16HA-107-D_179.png)
Power-Down Mode
Power-down is synchronously entered when CKE is registered LOW coincident with a
NOP or DES command. CKE is not allowed to go LOW while either an MRS, MPR,
ZQCAL, READ, or WRITE operation is in progress. CKE is allowed to go LOW while any
of the other legal operations (such as ROW ACTIVATION, PRECHARGE, auto precharge,
or REFRESH) are in progress. However, the power-down IDD specifications are not appli-
cable until such operations have been completed. Depending on the previous DRAM
state and the command issued prior to CKE going LOW, certain timing constraints must
be satisfied (as noted in
Table 80). Timing diagrams detailing the different power-down
Table 80: Command to Power-Down Entry Parameters
DRAM Status
Last Command Prior to
Parameter (Min)
Parameter Value
Figure
Idle or active
ACTIVATE
tACTPDEN
1tCK
Idle or active
PRECHARGE
tPRPDEN
1tCK
Active
READ or READAP
tRDPDEN
RL + 4tCK + 1tCK
Active
WRITE: BL8OTF, BL8MRS,
BC4OTF
tWRPDEN
WL + 4tCK + tWR/tCK
Active
WRITE: BC4MRS
WL + 2tCK + tWR/tCK
Active
WRITEAP: BL8OTF, BL8MRS,
BC4OTF
tWRAPDEN
WL + 4tCK + WR + 1tCK
Active
WRITEAP: BC4MRS
WL + 2tCK + WR + 1tCK
Idle
REFRESH
tREFPDEN
1tCK
Power-down
REFRESH
tXPDLL
Greater of 10tCK or 24ns
Idle
MODE REGISTER SET
tMRSPDEN
tMOD
Note: 1. If slow-exit mode precharge power-down is enabled and entered, ODT becomes asyn-
chronous tANPD prior to CKE going LOW and remains asynchronous until tANPD +
tXPDLL after CKE goes HIGH.
Entering power-down disables the input and output buffers, excluding CK, CK#, ODT,
CKE, and RESET#. NOP or DES commands are required until tCPDED has been satis-
fied, at which time all specified input/output buffers will be disabled. The DLL should
be in a locked state when power-down is entered for the fastest power-down exit tim-
ing. If the DLL is not locked during power-down entry, the DLL must be reset after
exiting power-down mode for proper READ operation as well as synchronous ODT op-
eration.
During power-down entry, if any bank remains open after all in-progress commands
are complete, the DRAM will be in active power-down mode. If all banks are closed af-
ter all in-progress commands are complete, the DRAM will be in precharge power-
down mode. Precharge power-down mode must be programmed to exit with either a
slow exit mode or a fast exit mode. When entering precharge power-down mode, the
DLL is turned off in slow exit mode or kept on in fast exit mode.
The DLL remains on when entering active power-down as well. ODT has special timing
constraints when slow exit mode precharge power-down is enabled and entered. Refer
2Gb: x4, x8, x16 DDR3 SDRAM
Power-Down Mode
PDF: 09005aef826aaadc
2Gb_DDR3_SDRAM.pdf – Rev. K 04/10 EN
179
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