Electrical Specifications – IDD Specifications and Conditions Definitions
Within the following IDD measurement tables, the following definitions and conditions
are used, unless stated otherwise:
LOW: VIN ≤ VIL(AC)max; HIGH: VIN ≥ VIH(AC)min
Midlevel: Inputs are VREF = VDD/2
RON set to RZQ/7 (34Ω)
RTT,nom set to RZQ/6 (40Ω)
RTT(WR) set to RZQ/2 (120Ω)
Qoff is enabled in MR1
ODT is enabled in MR1 (RTT,nom) and MR2 (RTT(WR))
TDQS is disabled in MR1
External DQ/DQS/DM load resister is 25Ω to VDDQ/2
Burst lengths are BL8 fixed
AL equals 0 (except in IDD7)
IDD specifications are tested after the device is properly initialized
Input slew rate is specified by AC parametric test conditions
Optional ASR is disabled
Read burst type uses nibble sequential (MR0 [3] 0)
Loop patterns must be executed at least once before current measurements begin
Table 9: Timing Parameters Used for IDD Measurements – Clock Units
IDD Parame-
ter
DDR3-800
DDR3-1066
DDR3-1333
DDR3-1600
DDR3-1866
Units
-25E
-25
-187E
-187
-15E
-15
-125E
-125
-107
5-5-5
6-6-6
7-7-7
8-8-8
9-9-9
10-10-10
11-11-11
13-13-13
tCK (MIN) IDD
2.5
1.875
1.5
1.25
1.07
ns
CL IDD
5
6
7
8
9
10
11
13
CK
tRCD (MIN)
IDD
5
6
7
8
9
10
11
13
CK
tRC (MIN) IDD
20
21
27
28
33
34
38
39
45
CK
tRAS (MIN)
IDD
15
20
24
28
32
CK
tRP (MIN)
5
6
7
8
9
10
11
13
CK
tFAW x4, x8
16
20
24
26
CK
x16
20
27
30
32
33
CK
tRRD
IDD
x4, x8
4
5
CK
x16
4
6
5
6
CK
tRFC
1Gb
44
59
74
88
103
CK
2Gb
64
86
107
128
150
CK
4Gb
120
160
200
240
281
CK
2Gb: x4, x8, x16 DDR3 SDRAM
Electrical Specifications – IDD Specifications and Conditions
Definitions
PDF: 09005aef826aaadc
2Gb_DDR3_SDRAM.pdf – Rev. K 04/10 EN
32
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