![](http://datasheet.mmic.net.cn/200000/MT41J128M16HA-107-D_datasheet_15084792/MT41J128M16HA-107-D_156.png)
burst.
Data from any READ burst must be completed before a subsequent WRITE burst is al-
lowed. An example of a READ burst followed by a WRITE burst for BL8 is shown in
completed before the write data is on the bus, the minimum READ-to-WRITE timing is
RL + tCCD - WL + 2tCK.
A READ burst may be followed by a PRECHARGE command to the same bank provided
auto precharge is not activated. The minimum READ-to-PRECHARGE command spac-
ing to the same bank is four clocks and must also satisfy a minimum analog time from
the READ command. This time is called tRTP (READ-to-PRECHARGE). tRTP starts AL
cycles later than the READ command. Examples for BL8 are shown in
Figure 73subsequent command to the same bank cannot be issued until tRP is met. The PRE-
CHARGE command followed by another PRECHARGE command to the same bank is
allowed. However, the precharge period will be determined by the last PRECHARGE
command issued to the bank.
If A10 is HIGH when a READ command is issued, the READ with auto precharge func-
tion is engaged. The DRAM starts an auto precharge operation on the rising edge, which
is AL + tRTP cycles after the READ command. DRAM support a tRAS lockout feature (see
auto precharge operation will be delayed until tRAS (MIN) is satisfied. If tRTP (MIN) is
not satisfied at the edge, the starting point of the auto precharge operation will be de-
layed until tRTP (MIN) is satisfied. In case the internal precharge is pushed out by tRTP,
tRP starts at the point at which the internal precharge happens (not at the next rising
clock edge after this event). The time from READ with auto precharge to the next ACTI-
VATE command to the same bank is AL + (tRTP + tRP)*, where * means rounded up to
the next integer. In any event, internal precharge does not start earlier than four clocks
after the last 8n-bit prefetch.
2Gb: x4, x8, x16 DDR3 SDRAM
READ Operation
PDF: 09005aef826aaadc
2Gb_DDR3_SDRAM.pdf – Rev. K 04/10 EN
156
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