![](http://datasheet.mmic.net.cn/200000/MT41J128M16HA-107-D_datasheet_15084792/MT41J128M16HA-107-D_168.png)
Figure 84: WRITE Burst
DI
n + 3
DI
n + 2
DI
n + 1
DI
n
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
Don’t Care
Transitioning Data
DI
n + 7
DI
n + 6
DI
n + 5
DI
n + 4
Bank,
Col n
NOP
WRITE
NOP
CK
CK#
Command1
DQ3
DQS, DQS#
Address2
tWPST
tWPRE
tWPST
tDQSL
DQ3
tWPST
DQS, DQS#
tDQSL
tWPRE
tDQSS
tDQSS tDSH
tDSH
tDSS
tDSH
tDQSL
tDQSH
tDQSL
tDQSH
tDQSL
tDQSH
tDQSH tDQSL
tDQSL
tDQSH
tDQSL
tDQSH
tDQSL
tDQSH
tDQSL
tDQSH
tDQSL
tDQSH
tDQSL
tDQSH
WL = AL + CWL
tDQSS (MIN)
tDQSS (NOM)
tDQSS (MAX)
tDQSL
tWPRE
DI
n + 3
DI
n + 2
DI
n + 1
DI
n
DI
n + 7
DI
n + 6
DI
n + 5
DI
n + 4
DI
n + 3
DI
n + 2
DI
n + 1
DI
n
DI
n + 7
DI
n + 6
DI
n + 5
DI
n + 4
Notes: 1. NOP commands are shown for ease of illustration; other commands may be valid at
these times.
2. The BL8 setting is activated by either MR0[1:0] = 00 or MR0[1:0] = 01 and A12 = 1 during
the WRITE command at T0.
3. DI n = data-in for column n.
4. BL8, WL = 5 (AL = 0, CWL = 5).
5. tDQSS must be met at each rising clock edge.
6. tWPST is usually depicted as ending at the crossing of DQS, DQS#; however, tWPST actual-
ly ends when DQS no longer drives LOW and DQS# no longer drives HIGH.
2Gb: x4, x8, x16 DDR3 SDRAM
WRITE Operation
PDF: 09005aef826aaadc
2Gb_DDR3_SDRAM.pdf – Rev. K 04/10 EN
168
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