Table 15: IDD4R Measurement Loop
CK,
CK#
CKE
Sub-loop
Cycle
Number
Command
CS#
RAS#
CAS#
WE#
ODT
BA[2:0]
A[15:11]
A[10]
A[9:7]
A[6:3]
A[2:0]
Data
Toggling
Static
HIGH
0
RD
0
1
0
1
0
00000000
1
D
1
0
–
2
D#
1
0
–
3
D#
1
0
–
4
RD
0
1
0
1
0
F
0
00110011
5
D
1
0
F
0
–
6
D#
1
0
F
0
–
7
D#
1
0
F
0
–
1
8–15
Repeat sub-loop 0, use BA[2:0] = 1
2
16–23
Repeat sub-loop 0, use BA[2:0] = 2
3
24–31
Repeat sub-loop 0, use BA[2:0] = 3
4
32–39
Repeat sub-loop 0, use BA[2:0] = 4
5
40–47
Repeat sub-loop 0, use BA[2:0] = 5
6
48–55
Repeat sub-loop 0, use BA[2:0] = 6
7
56–63
Repeat sub-loop 0, use BA[2:0] = 7
Notes: 1. DQ, DQS, DQS# are midlevel when not driving in burst sequence.
2. DM is LOW.
3. Burst sequence is driven on each DQ signal by the RD command.
4. All banks open.
2Gb: x4, x8, x16 DDR3 SDRAM
Electrical Specifications – IDD Specifications and Conditions
Definitions
PDF: 09005aef826aaadc
2Gb_DDR3_SDRAM.pdf – Rev. K 04/10 EN
37
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