![](http://datasheet.mmic.net.cn/200000/MT41J128M16HA-107-D_datasheet_15084792/MT41J128M16HA-107-D_166.png)
WRITE Operation
WRITE bursts are initiated with a WRITE command. The starting column and bank ad-
dresses are provided with the WRITE command, and auto precharge is either enabled
or disabled for that access. If auto precharge is selected, the row being accessed will be
precharged at the end of the WRITE burst. If auto precharge is not selected, the row will
remain open for subsequent accesses. After a WRITE command has been issued, the
WRITE burst may not be interrupted. For the generic WRITE commands used in
Fig-During WRITE bursts, the first valid data-in element is registered on a rising edge of
DQS following the WRITE latency (WL) clocks later and subsequent data elements will
be registered on successive edges of DQS. WRITE latency (WL) is defined as the sum of
POSTED CAS ADDITIVE latency (AL) and CAS WRITE latency (CWL): WL = AL + CWL.
The values of AL and CWL are programmed in the MR0 and MR2 registers, respectively.
Prior to the first valid DQS edge, a full cycle is needed (including a dummy crossover of
half cycle on DQS following the last data-in element is known as the WRITE postamble.
The time between the WRITE command and the first valid edge of DQS is WL clocks
(MAX) cases.
Data may be masked from completing a WRITE using data mask. The mask occurs on
the DM ball aligned to the write data. If DM is LOW, the write completes normally. If
DM is HIGH, that bit of data is masked.
Upon completion of a burst, assuming no other commands have been initiated, the DQ
will remain High-Z, and any additional input data will be ignored.
Data for any WRITE burst may be concatenated with a subsequent WRITE command to
provide a continuous flow of input data. The new WRITE command can be tCCD clocks
following the previous WRITE command. The first data element from the new burst is
Data for any WRITE burst may be followed by a subsequent READ command after tWTR
Data for any WRITE burst may be followed by a subsequent PRECHARGE command
Both tWTR and tWR starting time may vary depending on the mode register settings
(fixed BC4, BL8 versus OTF).
2Gb: x4, x8, x16 DDR3 SDRAM
WRITE Operation
PDF: 09005aef826aaadc
2Gb_DDR3_SDRAM.pdf – Rev. K 04/10 EN
166
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