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| 型号： | MT41J128M16HA-107:D |
| 元件分类： | DRAM |
| 英文描述： | 128M X 16 DDR DRAM, PBGA96 |
| 封装： | 9 X 14 MM, LEAD FREE, FBGA-96 |
| 文件页数： | 145/210页 |
| 文件大小： | 12448K |
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Input Clock Frequency Change ...................................................................................................................... 123
Write Leveling ............................................................................................................................................... 125
Write Leveling Procedure ........................................................................................................................... 127
Write Leveling Mode Exit Procedure ........................................................................................................... 129
Initialization ................................................................................................................................................. 130
Mode Registers .............................................................................................................................................. 132
Mode Register 0 (MR0) .................................................................................................................................. 133
Burst Length ............................................................................................................................................. 133
Burst Type ................................................................................................................................................ 134
DLL RESET ................................................................................................................................................ 135
Write Recovery .......................................................................................................................................... 135
Precharge Power-Down (Precharge PD) ..................................................................................................... 136
CAS Latency (CL) ....................................................................................................................................... 136
Mode Register 1 (MR1) .................................................................................................................................. 137
DLL Enable/DLL Disable ........................................................................................................................... 137
Output Drive Strength ............................................................................................................................... 138
OUTPUT ENABLE/DISABLE ...................................................................................................................... 138
TDQS Enable ............................................................................................................................................. 138
On-Die Termination .................................................................................................................................. 139
WRITE LEVELING ..................................................................................................................................... 139
POSTED CAS ADDITIVE Latency ................................................................................................................ 139
Mode Register 2 (MR2) .................................................................................................................................. 141
CAS Write Latency (CWL) ........................................................................................................................... 141
AUTO SELF REFRESH (ASR) ...................................................................................................................... 142
SELF REFRESH TEMPERATURE (SRT) ....................................................................................................... 142
SRT vs. ASR ............................................................................................................................................... 143
DYNAMIC ODT ......................................................................................................................................... 143
Mode Register 3 (MR3) .................................................................................................................................. 144
MULTIPURPOSE REGISTER (MPR) ............................................................................................................ 144
MPR Functional Description ...................................................................................................................... 145
MPR Register Address Definitions and Bursting Order ................................................................................ 146
MPR Read Predefined Pattern .................................................................................................................... 151
MODE REGISTER SET (MRS) Command ........................................................................................................ 151
ZQ CALIBRATION Operation ......................................................................................................................... 152
ACTIVATE Operation ..................................................................................................................................... 153
READ Operation ............................................................................................................................................ 155
WRITE Operation .......................................................................................................................................... 166
DQ Input Timing ....................................................................................................................................... 174
PRECHARGE Operation ................................................................................................................................. 176
SELF REFRESH Operation ............................................................................................................................. 176
Extended Temperature Usage ........................................................................................................................ 178
Power-Down Mode ....................................................................................................................................... 179
RESET Operation ........................................................................................................................................... 187
On-Die Termination (ODT) ........................................................................................................................... 189
Functional Representation of ODT ............................................................................................................. 189
Nominal ODT ........................................................................................................................................... 189
Dynamic ODT ............................................................................................................................................... 191
Functional Description .............................................................................................................................. 191
Synchronous ODT Mode ............................................................................................................................... 196
ODT Latency and Posted ODT ................................................................................................................... 196
Timing Parameters .................................................................................................................................... 196
ODT Off During READs .............................................................................................................................. 199
2Gb: x4, x8, x16 DDR3 SDRAM
PDF: 09005aef826aaadc
2Gb_DDR3_SDRAM.pdf – Rev. K 04/10 EN
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Micron Technology, Inc. reserves the right to change products or specifications without notice.
2006 Micron Technology, Inc. All rights reserved.
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