![](http://datasheet.mmic.net.cn/200000/MT41J128M16HA-107-D_datasheet_15084792/MT41J128M16HA-107-D_125.png)
Write Leveling
For better signal integrity, DDR3 SDRAM memory modules adopted fly-by topology for
the commands, addresses, control signals, and clocks. Write leveling is a scheme for the
memory controller to adjust or deskew the DQS strobe (DQS, DQS#) to CK relationship
at the DRAM with a simple feedback feature provided by the DRAM. Write leveling is
generally used as part of the initialization process, if required. For normal DRAM opera-
tion, this feature must be disabled. This is the only DRAM operation where the DQS
functions as an input (to capture the incoming clock) and the DQ function as outputs
(to report the state of the clock). Note that nonstandard ODT schemes are required.
The memory controller using the write leveling procedure must have adjustable delay
settings on its DQS strobe to align the rising edge of DQS to the clock at the DRAM pins.
This is accomplished when the DRAM asynchronously feeds back the CK status via the
DQ bus and samples with the rising edge of DQS. The controller repeatedly delays the
DQS strobe until a CK transition from 0 to 1 is detected. The DQS delay established
through this procedure helps ensure tDQSS, tDSS, and tDSH specifications in systems
that use fly-by topology by deskewing the trace length mismatch. A conceptual timing
of this procedure is shown.
Figure 46: Write Leveling Concept
CK
CK#
Source
Differential DQS
DQ
CK
CK#
Destination
Push DQS to capture
0–1 transition
T0
T1
T2
T3
T4
T5
T6
T7
T0
T1
T2
T3
T4
T5
T6
Tn
CK
CK#
T0
T1
T2
T3
T4
T5
T6
Tn
Don’t Care
1
0
2Gb: x4, x8, x16 DDR3 SDRAM
Write Leveling
PDF: 09005aef826aaadc
2Gb_DDR3_SDRAM.pdf – Rev. K 04/10 EN
125
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