tWR (ns) by tCK (ns) and rounding up a noninteger value to the next integer: WR (cycles)
= roundup (tWR [ns]/tCK [ns]).
Precharge Power-Down (Precharge PD)
The precharge PD bit applies only when precharge power-down mode is being used.
When MR0[12] is set to 0, the DLL is off during precharge power-down providing a low-
er standby current mode; however, tXPDLL must be satisfied when exiting. When
MR0[12] is set to 1, the DLL continues to run during precharge power-down mode to
enable a faster exit of precharge power-down mode; however, tXP must be satisfied
CAS Latency (CL)
lay, in clock cycles, between the internal READ command and the availability of the first
bit of output data. The CL can be set to 5, 6, 7, 8, 9, 10, 11, 12, or 13. DDR3 SDRAM do
not support half-clock latencies.
Examples of CL = 6 and CL = 8 are shown below. If an internal READ command is regis-
tered at clock edge n, and the CAS latency is m clocks, the data will be available
cate the CLs supported at various operating frequencies.
Figure 53: READ Latency
READ
NOP
CK
CK#
Command
DQ
DQS, DQS#
T0
T1
T2
T3
T4
T5
T6
T7
T8
Don’t Care
CK
CK#
Command
DQ
READ
NOP
T0
T1
T2
T3
T4
T5
T6
T7
T8
DI
n + 3
DI
n + 1
DI
n + 2
DI
n + 4
DI
n
DI
n
NOP
AL = 0, CL = 8
AL = 0, CL = 6
Transitioning Data
Notes: 1. For illustration purposes, only CL = 6 and CL = 8 are shown. Other CL values are possible.
2. Shown with nominal tDQSCK and nominal tDSDQ.
2Gb: x4, x8, x16 DDR3 SDRAM
Mode Register 0 (MR0)
PDF: 09005aef826aaadc
2Gb_DDR3_SDRAM.pdf – Rev. K 04/10 EN
136
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