![](http://datasheet.mmic.net.cn/200000/MT41J128M16HA-107-D_datasheet_15084792/MT41J128M16HA-107-D_159.png)
Figure 72: READ (BC4) to WRITE (BC4) OTF
Don’t Care
Transitioning Data
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
CK
CK#
Address2
Bank,
Col n
Bank,
Col b
Command1
READ
NOP
WRITE
NOP
tWPST
tWPRE
tRPST
DQS, DQS#
DQ3
WL = 5
READ-to-WRITE command delay = RL + tCCD/2 + 2tCK - WL
tWR
tWTR
tBL = 4 clocks
tRPRE
RL = 5
DO
n
DO
n+ 1
DO
n + 2
DO
n + 3
DI
n
DI
n + 1
DI
n + 2
DI
n + 3
Notes: 1. NOP commands are shown for ease of illustration; other commands may be valid at these times.
2. The BC4 OTF setting is activated by MR0[1:0] and A12 = 0 during READ command at T0 and WRITE command at T4.
3. DO n = data-out from column n; DI n = data-in from column b.
4. BC4, RL = 5 (AL - 0, CL = 5), WL = 5 (AL = 0, CWL = 5).
Figure 73: READ to PRECHARGE (BL8)
tRAS
tRTP
CK
CK#
Command
NOP
Address
DQ
DQS, DQS#
Don’t Care
Transitioning Data
NOP
ACT
NOP
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
NOP
READ
Bank a,
Col n
NOP
PRE
Bank a,
(or all)
Bank a,
Row b
tRP
DO
n
DO
n + 1
DO
n + 2
DO
n + 3
DO
n + 4
DO
n + 5
DO
n + 6
DO
n + 7
2Gb:
x4,
x8,
x16
DDR3
SDRAM
PDF:
09005aef826aaadc
2Gb_DDR3_SDRAM.pdf
–
Rev.
K
04/10
EN
159
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2006
Micron
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