![](http://datasheet.mmic.net.cn/200000/MT41J128M16HA-107-D_datasheet_15084792/MT41J128M16HA-107-D_132.png)
Mode Registers
Mode registers (MR0–MR3) are used to define various modes of programmable opera-
tions of the DDR3 SDRAM. A mode register is programmed via the mode register set
(MRS) command during initialization, and it retains the stored information (except for
MR0[8] which is self-clearing) until it is either reprogrammed, RESET# goes LOW, or
until the device loses power.
Contents of a mode register can be altered by reexecuting the MRS command. If the
user chooses to modify only a subset of the mode register’s variables, all variables must
be programmed when the MRS command is issued. Reprogramming the mode register
will not alter the contents of the memory array, provided it is performed correctly.
The MRS command can only be issued (or reissued) when all banks are idle and in the
precharged state (tRP is satisfied and no data bursts are in progress). After an MRS com-
mand has been issued, two parameters must be satisfied: tMRD and tMOD. The control-
ler must wait tMRD before initiating any subsequent MRS commands.
Figure 50: MRS to MRS Command Timing (tMRD)
Valid
MRS1
MRS2
NOP
T0
T1
T2
Ta0
Ta1
Ta2
CK#
CK
Command
Address
CKE3
Don’t Care
Indicates A Break in
Time Scale
tMRD
Notes: 1. Prior to issuing the MRS command, all banks must be idle and precharged, tRP (MIN)
must be satisfied, and no data bursts can be in progress.
2. tMRD specifies the MRS to MRS command minimum cycle time.
3. CKE must be registered HIGH from the MRS command until tMRSPDEN (MIN) (see Power- 4. For a CAS latency change, tXPDLL timing must be met before any nonMRS command.
The controller must also wait tMOD before initiating any nonMRS commands (exclud-
ing NOP and DES). The DRAM requires tMOD in order to update the requested features,
with the exception of DLL RESET, which requires additional time. Until tMOD has been
satisfied, the updated features are to be assumed unavailable.
2Gb: x4, x8, x16 DDR3 SDRAM
Mode Registers
PDF: 09005aef826aaadc
2Gb_DDR3_SDRAM.pdf – Rev. K 04/10 EN
132
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2006 Micron Technology, Inc. All rights reserved.