Functional Block Diagrams
DDR3 SDRAM is a high-speed, CMOS dynamic random access memory. It is internally
configured as an 8-bank DRAM.
Figure 3: 512 Meg x 4 Functional Block Diagram
Bank 5
Bank 6
Bank 7
Bank 4
Bank 7
Bank 4
Bank 5
Bank 6
15
Row-
address
MUX
Control
logic
Column-
address
counter/
latch
Mode registers
11
Command
decode
A[14:0]
BA[2:0]
15
Address
register
18
256
(x32)
8,192
I/O gating
DM mask logic
Column
decoder
Bank 0
memory
array
(32,768 x 256 x 32)
Bank 0
row-
address
latch
and
decoder
32,768
Sense amplifiers
Bank
control
logic
18
Bank 1
Bank 2
Bank 3
15
8
3
Refresh
counter
4
32
DQS, DQS#
Columns 0, 1, and 2
ZQCL, ZQCS
To pullup/pulldown
networks
READ
drivers
DQ[3:0]
READ
FIFO
and
data
MUX
Data
4
3
Bank 1
Bank 2
Bank 3
DM
CK,CK#
DQS, DQS#
ODT
control
ZQ CAL
WE#
ZQ
RZQ
CK, CK#
RAS#
CAS#
CS#
ODT
CKE
RESET#
CK,CK#
DLL
DQ[3:0]
(1 . . . 4)
(1, 2)
sw1
sw2
VDDQ/2
RTT,nom RTT(WR)
sw1
sw2
VDDQ/2
RTT,nom RTT(WR)
sw1
sw2
VDDQ/2
RTT,nom RTT(WR)
BC4
BC4 (burst chop)
BC4
Column 2
(select upper or
lower nibble for BC4)
Data
interface
WRITE
drivers
and
input
logic
A12
VSSQ
OTF
2Gb: x4, x8, x16 DDR3 SDRAM
Functional Block Diagrams
PDF: 09005aef826aaadc
2Gb_DDR3_SDRAM.pdf – Rev. K 04/10 EN
14
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