![](http://datasheet.mmic.net.cn/200000/MT41J128M16HA-107-D_datasheet_15084792/MT41J128M16HA-107-D_83.png)
Table 56: Electrical Characteristics and AC Operating Conditions (Continued)
Notes 1–8 apply to the entire table
Parameter
Symbol
DDR3-800
DDR3-1066
DDR3-1333
DDR3-1600
Units Notes
Min
Max
Min
Max
Min
Max
Min
Max
ODT Timing
RTT synchronous turn-on delay
ODTL on
CWL + AL - 2CK
CK
RTT synchronous turn-off delay
ODTL off
CWL + AL - 2CK
CK
RTT turn-on from ODTL on reference
tAON
–400
400
–300
300
–250
250
–225
225
ps
RTT turn-off from ODTL off reference
tAOF
0.3
0.7
0.3
0.7
0.3
0.7
0.3
0.7
CK
Asynchronous RTT turn-on delay
(power-down with DLL off)
tAONPD
MIN = 2; MAX = 8.5
ns
Asynchronous RTT turn-off delay
(power-down with DLL off)
tAOFPD
MIN = 2; MAX = 8.5
ns
ODT HIGH time with WRITE command and BL8
ODTH8
MIN = 6; MAX = n/a
CK
ODT HIGH time without WRITE command or
with WRITE command and BC4
ODTH4
MIN = 4; MAX = n/a
CK
Dynamic ODT Timing
RTT,nom-to-RTT(WR) change skew
ODTLcnw
WL - 2CK
CK
RTT(WR)-to-RTT,nom change skew - BC4
ODTLcnw4
4CK + ODTL off
CK
RTT(WR)-to-RTT,nom change skew - BL8
ODTLcnw8
6CK + ODTL off
CK
RTT dynamic change skew
tADC
0.3
0.7
0.3
0.7
0.3
0.7
0.3
0.7
CK
Write Leveling Timing
First DQS, DQS# rising edge
tWLMRD
40
–
40
–
40
–
40
–
CK
DQS, DQS# delay
tWLDQSEN
25
–
25
–
25
–
25
–
CK
Write leveling setup from rising CK, CK#
crossing to rising DQS, DQS# crossing
tWLS
325
–
245
–
195
–
165
–
ps
Write leveling hold from rising DQS, DQS#
crossing to rising CK, CK# crossing
tWLH
325
–
245
–
195
–
165
–
ps
Write leveling output delay
tWLO
0
9
0
9
0
9
0
7.5
ns
Write leveling output error
tWLOE
0
2
0
2
0
2
0
2
ns
2Gb:
x4,
x8,
x16
DDR3
SDRAM
Electrical
Characteristics
and
AC
Operating
Conditions
PDF:
09005aef826aaadc
2Gb_DDR3_SDRAM.pdf
–
Rev.
K
04/10
EN
83
Micron
Technology,
Inc.
reserves
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right
to
change
products
or
specifications
without
notice.
2006
Micron
Technology,
Inc.
All
rights
reserved.