![](http://datasheet.mmic.net.cn/200000/MT41J128M16HA-107-D_datasheet_15084792/MT41J128M16HA-107-D_129.png)
Write Leveling Mode Exit Procedure
After the DRAM are leveled, they must exit from write leveling mode before the normal
leveling mode. After the last rising DQS (capturing a 1 at T0), the memory controller
should stop driving the DQS signals after tWLO (MAX) delay plus enough delay to ena-
ble the memory controller to capture the applicable prime DQ state (at ~Tb0). The DQ
balls become undefined when DQS no longer remains LOW, and they remain unde-
fined until tMOD after the MRS command (at Te1).
The ODT input should be deasserted LOW such that ODTL off (MIN) expires after the
DQS is no longer driving LOW. When ODT LOW satisfies tIS, ODT must be kept LOW (at
~Tb0) until the DRAM is ready for either another rank to be leveled or until the normal
mode can be used. After DQS termination is switched off, write level mode should be
disabled via the MRS command (at Tc2). After tMOD is satisfied (at Te1), any valid com-
mand may be registered by the DRAM. Some MRS commands may be issued after
tMRD (at Td1).
Figure 48: Exit Write Leveling
NOP
CK
T0
T1
T2
Ta0
Tb0
Tc0
Tc1
Tc2
Td0
Td1
Te0
Te1
CK#
Command
ODT
RTT(DQ)
NOP
MRS
NOP
Address
MR1
Valid
Don’t Care
Transitioning
RTT DQS, RTT DQS#
RTT,nom
Undefined Driving Mode
tAOF (MAX)
tMRD
Indicates a break in
time scale
DQS, DQS#
CK = 1
DQ
tIS
tAOF (MIN)
tMOD
tWLO + tWLOE
ODTL off
Note: 1. The DQ result, = 1, between Ta0 and Tc0, is a result of the DQS, DQS# signals capturing
CK HIGH just after the T0 state.
2Gb: x4, x8, x16 DDR3 SDRAM
Write Leveling
PDF: 09005aef826aaadc
2Gb_DDR3_SDRAM.pdf – Rev. K 04/10 EN
129
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