Figure 45: Change Frequency During Precharge Power-Down
CK
CK#
Command
NOP
Address
CKE
DQ
DM
DQS, DQS#
NOP
tCK
Enter precharge
power-down mode
Exit precharge
power-down mode
T0
T1
Ta0
Tc0
Tb0
T2
Don’t Care
tCKE
tXP
MRS
DLL RESET
Valid
NOP
tCH
tIH
tIS
tCL
Tc1
Td0
Te1
Td1
tCKSRE
tCH
b
tCL
b
tCK
b
tCH
b
tCL
b
tCK
b
tCH
b
tCL
b
tCK
b
tCPDED
ODT
NOP
Te0
Previous clock frequency
New clock frequency
Frequency
change
Indicates A Break in
Time Scale
tIH
tIS
tIH
tIS
tDLLK
tAOFPD/tAOF
tCKSRX
High-Z
Notes: 1. Applicable for both SLOW-EXIT and FAST-EXIT precharge power-down modes.
2. tAOFPD and tAOF must be satisfied and outputs High-Z prior to T1 (see On-Die Termina- 3. If the RTT,nom feature was enabled in the mode register prior to entering precharge power-
down mode, the ODT signal must be continuously registered LOW ensuring RTT is in an
off state. If the RTT,nom feature was disabled in the mode register prior to entering pre-
charge power-down mode, RTT will remain in the off state. The ODT signal can be
registered either LOW or HIGH in this case.
2Gb: x4, x8, x16 DDR3 SDRAM
Input Clock Frequency Change
PDF: 09005aef826aaadc
2Gb_DDR3_SDRAM.pdf – Rev. K 04/10 EN
124
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