Figure 70: Nonconsecutive READ Bursts
Don’t Care
Transitioning Data
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
DQS, DQS#
Command
NOP
READ
NOP
READ
Address
Bank a,
Col n
Bank a,
Col b
CK
CK#
DQ
DO
n
DO
b
CL = 8
Notes: 1. AL = 0, RL = 8.
2. DO n (or b) = data-out from column n (or column b).
3. Seven subsequent elements of data-out appear in the programmed order following DO n.
4. Seven subsequent elements of data-out appear in the programmed order following DO b.
Figure 71: READ (BL8) to WRITE (BL8)
Don’t Care
Transitioning Data
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
CK
CK#
Command1
NOP
WRITE
NOP
tWPST
tRPRE
tWPRE
tRPST
DQS, DQS#
DQ3
WL = 5
tWR
tWTR
READ
DO
n
DO
n + 1
DO
n + 2
DO
n + 3
DO
n + 4
DO
n + 5
DO
n + 6
DO
n + 7
DI
n
DI
n + 1
DI
n + 2
DI
n + 3
DI
n + 4
DI
n + 5
DI
n + 6
DI
n + 7
READ-to-WRITE command delay = RL + tCCD + 2tCK - WL
tBL = 4 clocks
Address2
Bank,
Col b
Bank,
Col n
RL = 5
Notes: 1. NOP commands are shown for ease of illustration; other commands may be valid at these times.
2. The BL8 setting is activated by either MR0[1:0] = 00 or MR0[1:0] = 01 and A12 = 1 during the READ command at
T0, and the WRITE command at T6.
3. DO n = data-out from column, DI b = data-in for column b.
4. BL8, RL = 5 (AL = 0, CL = 5), WL = 5 (AL = 0, CWL = 5).
2Gb:
x4,
x8,
x16
DDR3
SDRAM
PDF:
09005aef826aaadc
2Gb_DDR3_SDRAM.pdf
–
Rev.
K
04/10
EN
158
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2006
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