Figure 112: Dynamic ODT: ODT Pin Asserted with WRITE Command for 6 Clock Cycles, BC4
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
ODTL on
ODTLcnw
WL
T10
T11
CK
CK#
ODTLcwn 4
DQS, DQS#
Address
Valid
Don’t Care
Transitioning
ODTL off
Command
WRS4
NOP
DQ
DI
n + 3
DI
n + 2
DI
n + 1
DI
n
tADC (MIN)
tAOF (MIN)
tAOF (MAX)
tADC (MAX)
tAON (MIN)
ODTH4
ODT
RTT
RTT(WR)
RTT,nom
Notes: 1. Via MRS or OTF. AL = 0, CWL = 5. RTT,nom and RTT(WR) are enabled.
2. ODTH4 is defined from ODT registered HIGH to ODT registered LOW, so in this example,
ODTH4 is satisfied. ODT registered LOW at T5 is also legal.
Figure 113: Dynamic ODT: ODT Pin Asserted with WRITE Command for 4 Clock Cycles, BC4
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
ODTL on
ODTLcnw
WL
T10
T11
CK
CK#
ODTLcwn 4
DQS, DQS#
Address
Valid
Rtt _wr
Command
WRS4
NOP
Don’t Care
Transitioning
DQ
DI
n
DI
n + 3
DI
n + 2
DI
n + 1
ODTH4
tADC (MAX)
tAON (MIN)
tAOF (MIN)
tAOF (MAX)
ODTL off
RTT
RTT(WR)
ODT
Notes: 1. Via MRS or OTF. AL = 0, CWL = 5. RTT,nom can be either enabled or disabled. If disabled,
ODT can remain HIGH. RTT(WR) is enabled.
2. In this example ODTH4 = 4 is satisfied exactly.
2Gb: x4, x8, x16 DDR3 SDRAM
PDF: 09005aef826aaadc
2Gb_DDR3_SDRAM.pdf – Rev. K 04/10 EN
195
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