Output Characteristics and Operating Conditions
The DRAM uses both single-ended and differential output drivers. The single-ended out-
put driver is summarized below, while the differential output driver is summarized in
Table 48: Single-Ended Output Driver Characteristics
All voltages are referenced to VSS
Parameter/Condition
Symbol
Min
Max
Units
Notes
Output leakage current: DQ are disabled;
0V
≤ VOUT ≤ VDDQ; ODT is disabled; ODT is HIGH
IOZ
–5
+5
A
Output slew rate: Single-ended; For rising and falling edges,
measure between VOL(AC) = VREF - 0.1 × VDDQ and VOH(AC) =
VREF + 0.1 × VDDQ
SRQse
2.5
6
V/ns
Single-ended DC high-level output voltage
VOH(DC)
0.8 × VDDQ
V
Single-ended DC mid-point level output voltage
VOM(DC)
0.5 × VDDQ
V
Single-ended DC low-level output voltage
VOL(DC)
0.2 × VDDQ
V
Single-ended AC high-level output voltage
VOH(AC)
VTT + 0.1 × VDDQ
V
Single-ended AC low-level output voltage
VOL(AC)
VTT - 0.1 × VDDQ
V
Delta Ron between pull-up and pull-down for DQ/DQS
MMPUPD
–10
+10
%
Test load for AC timing and output slew rates
Output to VTT (VDDQ/2) via 25Ω resistor
Notes: 1. RZQ of
240Ω (±1%) with RZQ/7 enabled (default 34Ω driver) and is applicable after prop-
er ZQ calibration has been performed at a stable temperature and voltage (VDDQ = VDD,
VSSQ = VSS).
2. VTT = VDDQ/2.
4. The 6 V/ns maximum is applicable for a single DQ signal when it is switching either from
HIGH to LOW or LOW to HIGH while the remaining DQ signals in the same byte lane are
either all static or all switching the opposite direction. For all other DQ signal switching
combinations, the maximum limit of 6 V/ns is reduced to 5 V/ns.
2Gb: x4, x8, x16 DDR3 SDRAM
Output Characteristics and Operating Conditions
PDF: 09005aef826aaadc
2Gb_DDR3_SDRAM.pdf – Rev. K 04/10 EN
69
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