![](http://datasheet.mmic.net.cn/200000/MT41J128M16HA-107-D_datasheet_15084792/MT41J128M16HA-107-D_123.png)
Input Clock Frequency Change
When the DDR3 SDRAM is initialized, it requires the clock to be stable during most nor-
mal states of operation. This means that after the clock frequency has been set to the
stable state, the clock period is not allowed to deviate except what is allowed for by the
clock jitter and spread spectrum clocking (SSC) specifications.
The input clock frequency can be changed from one stable clock rate to another under
two conditions: self refresh mode and precharge power-down mode. Outside of these
two modes, it is illegal to change the clock frequency. For the self refresh mode condi-
tion, when the DDR3 SDRAM has been successfully placed into self refresh mode and
tCKSRE has been satisfied, the state of the clock becomes a “Don’t Care.” When the
clock becomes a “Don’t Care,” changing the clock frequency is permissible, provided
the new clock frequency is stable prior to tCKSRX. When entering and exiting self re-
fresh mode for the sole purpose of changing the clock frequency, the self refresh entry
and exit specifications must still be met.
The precharge power-down mode condition is when the DDR3 SDRAM is in precharge
power-down mode (either fast exit mode or slow exit mode). Either ODT must be at a
logic LOW or RTT,nom and RTT(WR) must be disabled via MR1 and MR2. This ensures
RTT,nom and RTT(WR) are in an off state prior to entering precharge power-down mode,
and CKE must be at a logic LOW. A minimum of tCKSRE must occur after CKE goes
LOW before the clock frequency can change. The DDR3 SDRAM input clock frequency
is allowed to change only within the minimum and maximum operating frequency speci-
fied for the particular speed grade (tCK [AVG] MIN to tCK [AVG] MAX). During the input
clock frequency change, CKE must be held at a stable LOW level. When the input clock
frequency is changed, a stable clock must be provided to the DRAM tCKSRX before pre-
charge power-down may be exited. After precharge power-down is exited and tXP has
been satisfied, the DLL must be reset via the MRS. Depending on the new clock frequen-
cy, additional MRS commands may need to be issued. During the DLL lock time,
RTT,nom and RTT(WR) must remain in an off state. After the DLL lock time, the DRAM is
ready to operate with a new clock frequency.
2Gb: x4, x8, x16 DDR3 SDRAM
Input Clock Frequency Change
PDF: 09005aef826aaadc
2Gb_DDR3_SDRAM.pdf – Rev. K 04/10 EN
123
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