![](http://datasheet.mmic.net.cn/200000/MT41J128M16HA-107-D_datasheet_15084792/MT41J128M16HA-107-D_173.png)
Figure 91: WRITE (BL8) to PRECHARGE
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
Ta0
Ta1
DI
n + 3
DI
n + 2
DI
n + 1
DI
n
DI
n + 6
DI
n + 7
DI
n + 5
DI
n + 4
NOP
WRITE
Valid
NOP
PRE
CK
CK#
Command
DQ BL8
DQS, DQS#
Address
Don’t Care
Transitioning Data
Indicates A Break in
Time Scale
tWR
WL = AL + CWL
Valid
Notes: 1. DI n = data-in from column n.
2. Seven subsequent elements of data-in are applied in the programmed order following
DO n.
3. Shown for WL = 7 (AL = 0, CWL = 7).
Figure 92: WRITE (BC4 Mode Register Setting) to PRECHARGE
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
Ta0
Ta1
DI
n + 3
DI
n + 2
DI
n + 1
DI
n
NOP
WRITE
Valid
NOP
PRE
CK
CK#
Command
DQ BC4
DQS, DQS#
Address
Don’t Care
Transitioning Data
Indicates A Break in
Time Scale
tWR
WL = AL + CWL
Valid
Notes: 1. NOP commands are shown for ease of illustration; other commands may be valid at
these times.
2. The write recovery time (tWR) is referenced from the first rising clock edge after the last
write data is shown at T7. tWR specifies the last burst WRITE cycle until the PRECHARGE
command can be issued to the same bank.
3. The fixed BC4 setting is activated by MR0[1:0] = 10 during the WRITE command at T0.
4. DI n = data-in for column n.
5. BC4 (fixed), WL = 5, RL = 5.
2Gb: x4, x8, x16 DDR3 SDRAM
PDF: 09005aef826aaadc
2Gb_DDR3_SDRAM.pdf – Rev. K 04/10 EN
173
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