![](http://datasheet.mmic.net.cn/200000/MT41J128M16HA-107-D_datasheet_15084792/MT41J128M16HA-107-D_11.png)
State Diagram
Figure 2: Simplified State Diagram
SRX = Self refresh exit
WRITE = WR, WRS4, WRS8
WRITE AP = WRAP, WRAPS4, WRAPS8
ZQCL = ZQ LONG CALIBRATION
ZQCS = ZQ SHORT CALIBRATION
Bank
active
Reading
Writing
Activating
Refreshing
Self
refresh
Idle
Active
power-
down
ZQ
calibration
From any
state
Power
applied
Reset
procedure
Power
on
Initialization
MRS, MPR,
write
leveling
Precharge
power-
down
Writing
Reading
Automatic
sequence
Command
sequence
Precharging
READ
READ AP
PRE, PREA
WRITE
CKE L
WRITE
WRITE AP
PDE
PDX
SRX
SRE
REF
MRS
ACT
RESET
ZQCL
ZQCL/ZQCS
ACT = ACTIVATE
MPR = Multipurpose register
MRS = Mode register set
PDE = Power-down entry
PDX = Power-down exit
PRE = PRECHARGE
PREA = PRECHARGE ALL
READ = RD, RDS4, RDS8
READ AP = RDAP, RDAPS4, RDAPS8
REF = REFRESH
RESET = START RESET PROCEDURE
SRE = Self refresh entry
2Gb: x4, x8, x16 DDR3 SDRAM
State Diagram
PDF: 09005aef826aaadc
2Gb_DDR3_SDRAM.pdf – Rev. K 04/10 EN
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