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参数资料
| 型号： | MT41J128M16HA-107:D |
| 元件分类： | DRAM |
| 英文描述： | 128M X 16 DDR DRAM, PBGA96 |
| 封装： | 9 X 14 MM, LEAD FREE, FBGA-96 |
| 文件页数： | 36/210页 |
| 文件大小： | 12448K |
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Initialization
The following sequence is required for power up and initialization, as shown in Fig-
1. Apply power. RESET# is recommended to be below 0.2 × VDDQ during power ramp
to ensure the outputs remain disabled (High-Z) and ODT off (RTT is also High-Z).
All other inputs, including ODT, may be undefined.
During power-up, either of the following conditions may exist and must be met:
Condition A:
– VDD and VDDQ are driven from a single-power converter output and are ram-
ped with a maximum delta voltage between them of
ΔV ≤ 300mV. Slope
reversal of any power supply signal is allowed. The voltage levels on all balls
other than VDD, VDDQ, VSS, VSSQ must be less than or equal to VDDQ and VDD on
one side, and must be greater than or equal to VSSQ and VSS on the other side.
– Both VDD and VDDQ power supplies ramp to VDD,min and VDDQ,min within
tVDDPR = 200ms.
– VREFDQ tracks VDD × 0.5, VREFCA tracks VDD × 0.5.
– VTT is limited to 0.95V when the power ramp is complete and is not applied
directly to the device; however, tVTD should be greater than or equal to zero to
avoid device latchup.
Condition B:
– VDD may be applied before or at the same time as VDDQ.
– VDDQ may be applied before or at the same time as VTT, VREFDQ, and VREFCA.
– No slope reversals are allowed in the power supply ramp for this condition.
2. Until stable power, maintain RESET# LOW to ensure the outputs remain disabled
(High-Z). After the power is stable, RESET# must be LOW for at least 200s to be-
gin the initialization process. ODT will remain in the High-Z state while RESET# is
LOW and until CKE is registered HIGH.
3. CKE must be LOW 10ns prior to RESET# transitioning HIGH.
4. After RESET# transitions HIGH, wait 500s (minus one clock) with CKE LOW.
5. After this CKE LOW time, CKE may be brought HIGH (synchronously) and only
NOP or DES commands may be issued. The clock must be present and valid for at
least 10ns (and a minimum of five clocks) and ODT must be driven LOW at least
tIS prior to CKE being registered HIGH. When CKE is registered HIGH, it must be
continuously registered HIGH until the full initialization process is complete.
6. After CKE is registered HIGH and after tXPR has been satisfied, MRS commands
may be issued. Issue an MRS (LOAD MODE) command to MR2 with the applicable
settings (provide LOW to BA2 and BA0 and HIGH to BA1).
7. Issue an MRS command to MR3 with the applicable settings.
8. Issue an MRS command to MR1 with the applicable settings, including enabling
the DLL and configuring ODT.
9. Issue an MRS command to MR0 with the applicable settings, including a DLL RE-
SET command. tDLLK (512) cycles of clock input are required to lock the DLL.
10. Issue a ZQCL command to calibrate RTT and RON values for the process voltage
temperature (PVT). Prior to normal operation, tZQinit must be satisfied.
11. When tDLLK and tZQinit have been satisfied, the DDR3 SDRAM will be ready for
normal operation.
2Gb: x4, x8, x16 DDR3 SDRAM
Initialization
PDF: 09005aef826aaadc
2Gb_DDR3_SDRAM.pdf – Rev. K 04/10 EN
130
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2006 Micron Technology, Inc. All rights reserved.
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