Figure 95: Self Refresh Entry/Exit Timing
CK
CK#
Command
NOP
NOP4
SRE (REF)3
Address
CKE
ODT2
RESET#2
Valid
Valid6
SRX (NOP)
NOP5
tRP8
tXS6, 9
tXSDLL7, 9
ODTL
tIS
tCPDED
tIS
Enter self refresh mode
(synchronous)
Exit self refresh mode
(asynchronous)
T0
T1
T2
Tc0
Tc1
Td0
Tb0
Don’t Care
Te0
Valid
Valid7
Valid
tIH
Ta0
Tf0
Indicates A Break in
Time Scale
tCKSRX1
tCKSRE1
tCKESR (MIN)1
Notes: 1. The clock must be valid and stable meeting tCK specifications at least tCKSRE after enter-
ing self refresh mode, and at least tCKSRX prior to exiting self refresh mode, if the clock
is stopped or altered between states Ta0 and Tb0. If the clock remains valid and un-
changed from entry and during self refresh mode, then tCKSRE and tCKSRX do not
apply; however, tCKESR must be satisfied prior to exiting at SRX.
2. ODT must be disabled and RTT off prior to entering self refresh at state T1. If both
RTT,nom and RTT(WR) are disabled in the mode registers, ODT can be a “Don’t Care.”
3. Self refresh entry (SRE) is synchronous via a REFRESH command with CKE LOW.
4. A NOP or DES command is required at T2 after the SRE command is issued prior to the
inputs becoming “Don’t Care.”
5. NOP or DES commands are required prior to exiting self refresh mode until state Te0.
6. tXS is required before any commands not requiring a locked DLL.
7. tXSDLL is required before any commands requiring a locked DLL.
8. The device must be in the all banks idle state prior to entering self refresh mode. For
example, all banks must be precharged, tRP must be met, and no data bursts can be in
progress.
9. Self refresh exit is asynchronous; however, tXS and tXSDLL timings start at the first rising
clock edge where CKE HIGH satisfies tISXR at Tc1. tCKSRX timing is also measured so that
tISXR is satisfied at Tc1.
2Gb: x4, x8, x16 DDR3 SDRAM
SELF REFRESH Operation
PDF: 09005aef826aaadc
2Gb_DDR3_SDRAM.pdf – Rev. K 04/10 EN
177
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2006 Micron Technology, Inc. All rights reserved.