![](http://datasheet.mmic.net.cn/200000/MT41J128M16HA-107-D_datasheet_15084792/MT41J128M16HA-107-D_207.png)
Asynchronous to Synchronous ODT Mode Transition (Short CKE Pulse)
If the time in the precharge power down or idle states is very short (short CKE LOW
pulse), the power-down entry and power-down exit transition periods will overlap.
When overlap occurs, the response of the DRAM’s RTT to a change in the ODT state may
be synchronous or asynchronous from the start of the power-down entry transition pe-
riod to the end of the power-down exit transition period even if the entry period ends
later than the exit period.
If the time in the idle state is very short (short CKE HIGH pulse), the power-down exit
and power-down entry transition periods overlap. When this overlap occurs, the re-
sponse of the DRAM’s RTT to a change in the ODT state may be synchronous or
asynchronous from the start of power-down exit transition period to the end of the power-
down entry transition period.
2Gb: x4, x8, x16 DDR3 SDRAM
PDF: 09005aef826aaadc
2Gb_DDR3_SDRAM.pdf – Rev. K 04/10 EN
207
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2006 Micron Technology, Inc. All rights reserved.