Input/Output Capacitance
Table 7: Input/Output Capacitance
Note 1 applies to the entire table
Capacitance
Parameters
Symbol
DDR3-800 DDR3-1066 DDR3-1333 DDR3-1600 DDR3-1866
Units Notes
Min Max Min Max Min Max Min Max Min Max
CK and CK#
CCK
0.8
1.6
0.8
1.6
0.8
1.4
0.8
1.4
0.8
1.3
pF
ΔC: CK to CK#
CDCK
0
0.15
0
0.15
0
0.15
0
0.15
0
0.15
pF
Single-end I/O: DQ, DM
CIO
1.5
3.0
1.5
3.0
1.5
2.5
1.5
2.3
1.4
2.2
pF
Differential I/O: DQS,
DQS#, TDQS, TDQS#
CIO
1.5
3.0
1.5
3.0
1.5
2.5
1.5
2.3
1.4
2.2
pF
ΔC: DQS to DQS#, TDQS,
TDQS#
CDDQS
0
0.2
0
0.2
0
0.15
0
0.15
0
0.15
pF
ΔC: DQ to DQS
CDIO
–0.5
0.3
–0.5
0.3
–0.5
0.3
–0.5
0.3
–0.5
0.3
pF
Inputs (CTRL, CMD,
ADDR)
CI
0.75
1.4
0.75 1.35 0.75
1.3
0.75
1.3
0.75
1.3
pF
ΔC: CTRL to CK
CDI_CTRL
–0.5
0.3
–0.5
0.3
–0.4
0.2
–0.4
0.2
–0.4
0.2
pF
ΔC: CMD_ADDR to CK
CDI_CMD_ADDR –0.5
0.5
–0.5
0.5
–0.4
0.4
–0.4
0.4
–0.5
0.3
pF
ZQ pin capacitance
CZO
–
3.0
–
3.0
–
3.0
–
3.0
–
3.0
pF
Reset pin capacitance
CRE
–
3.0
–
3.0
–
3.0
–
3.0
–
3.0
pF
Notes: 1. VDD = +1.5V ±0.075mV, VDDQ = VDD, VREF = VSS, f = 100 MHz, TC = 25°C. VOUT(DC) = 0.5 ×
VDDQ, VOUT (peak-to-peak) = 0.1V.
2. DM input is grouped with I/O pins, reflecting the fact that they are matched in loading.
3. Includes TDQS, TDQS#. Cddqs is for DQS vs. DQS# and TDQS vs. TDQS# separately.
4. CDIO = CIO (DQ) - 0.5 × (CIO [DQS] + CIO [DQS#]).
5. Excludes CK, CK#; CTRL = ODT, CS#, and CKE; CMD = RAS#, CAS#, and WE#; ADDR = A[n:
0], BA[2:0].
6. CDI_CTRL = CI (CTRL) - 0.5 × (CCK [CK] + CCK [CK#]).
7. CDI_CMD_ADDR = CI (CMD_ADDR) - 0.5 × (CCK [CK] + CCK [CK#]).
2Gb: x4, x8, x16 DDR3 SDRAM
Electrical Specifications
PDF: 09005aef826aaadc
2Gb_DDR3_SDRAM.pdf – Rev. K 04/10 EN
30
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