![](http://datasheet.mmic.net.cn/200000/MT41J128M16HA-107-D_datasheet_15084792/MT41J128M16HA-107-D_162.png)
Figure 77: Data Output Timing – tDQSQ and Data Valid Window
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
Bank,
Col n
tRPST
NOP
READ
NOP
CK
CK#
Command1
Address 2
tDQSQ (MAX)
DQS, DQS#
DQ3 (last data valid)
DQ3 (first data no longer valid)
All DQ collectively
DO
n
DO
n + 3
DO
n + 2
DO
n + 1
DO
n + 7
DO
n + 6
DO
n + 5
DO
n + 4
DO
n + 2
DO
n + 1
DO
n + 7
DO
n + 6
DO
n + 5
DO
n + 4
DO
n + 3
DO
n + 2
DO
n + 1
DO
n
DO
n + 7
DO
n + 6
DO
n + 5
DO
n
DO
n + 3
tRPRE
Don’t Care
Transitioning Data
Data valid
tQH
tHZ (DQ) MAX
DO
n + 4
RL = AL + CL
tDQSQ (MAX)
tLZ (DQ) MIN
Notes: 1. NOP commands are shown for ease of illustration; other commands may be valid at these times.
2. The BL8 setting is activated by either MR0[1, 0] = 0, 0 or MR0[0, 1] = 0, 1 and A12 = 1 during READ command at T0.
3. DO n = data-out from column n.
4. BL8, RL = 5 (AL = 0, CL = 5).
5. Output timings are referenced to VDDQ/2 and DLL on and locked.
6. tDQSQ defines the skew between DQS, DQS# to data and does not define DQS, DQS# to clock.
7. Early data transitions may not always happen at the same DQ. Data transitions of a DQ can vary (either early or
late) within a burst.
2Gb:
x4,
x8,
x16
DDR3
SDRAM
PDF:
09005aef826aaadc
2Gb_DDR3_SDRAM.pdf
–
Rev.
K
04/10
EN
162
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