![](http://datasheet.mmic.net.cn/200000/MT41J128M16HA-107-D_datasheet_15084792/MT41J128M16HA-107-D_15.png)
Figure 4: 256 Meg x 8 Functional Block Diagram
Bank 5
Bank 6
Bank 7
Bank 4
Bank 7
Bank 4
Bank 5
Bank 6
15
Row-
address
MUX
Control
logic
Column-
address
counter/
latch
Mode registers
10
Command
decode
A[14:0]
BA[2:0]
15
18
8,192
I/O gating
DM mask logic
Column
decoder
Bank 0
Memory
array
(32,768 x 128 x 64)
Bank 0
row-
address
latch
and
decoder
32,768
Sense amplifiers
Bank
control
logic
18
Bank 1
Bank 2
Bank 3
15
7
3
Refresh
counter
8
64
DQS, DQS#
Columns 0, 1, and 2
ZQCL, ZQCS
To ODT/output drivers
Read
drivers
DQ[7:0]
READ
FIFO
and
data
MUX
Data
8
3
Bank 1
Bank 2
Bank 3
DM/TDQS
(shared pin)
TDQS#
CK, CK#
DQS/DQS#
ZQ CAL
ZQ
RZQ
ODT
CKE
CK, CK#
RAS#
WE#
CAS#
CS#
RESET#
CK, CK#
DLL
DQ[7:0]
DQ8
(1 . . . 8)
(1, 2)
sw1
sw2
VDDQ/2
RTT(WR)
RTT,nom
sw1
sw2
VDDQ/2
RTT,nom RTT(WR)
sw1
sw2
VDDQ/2
RTT,nom RTT(WR)
BC4 (burst chop)
BC4
Write
drivers
and
input
logic
Data
interface
Column 2
(select upper or
lower nibble for BC4)
(128
x64)
ODT
control
Address
register
A12
VSSQ
OTF
Figure 5: 128 Meg x 16 Functional Block Diagram
Bank 5
Bank 6
Bank 7
Bank 4
Bank 7
Bank 4
Bank 5
Bank 6
13
Row-
address
MUX
Control
logic
Column-
address
counter/
latch
Mode registers
10
Command
decode
A[13:0]
BA[2:0]
14
Address
register
17
(128
x128)
16,384
I/O gating
DM mask logic
Column
decoder
Bank 0
memory
array
(16,384 x 128 x 128)
Bank 0
row-
address
latch
and
decoder
16,384
Sense amplifiers
Bank
control
logic
17
Bank 1
Bank 2
Bank 3
14
7
3
Refresh
counter
16
128
LDQS, LDQS#, UDQS, UDQS#
Column 0, 1, and 2
Columns 0, 1, and 2
ZQCL, ZQCS
To ODT/output drivers
BC4
READ
drivers
DQ[15:0]
READ
FIFO
and
data
MUX
Data
16
BC4 (burst chop)
3
Bank 1
Bank 2
Bank 3
LDM/UDM
CK, CK#
LDQS, LDQS#
UDQS, UDQS#
ZQ CAL
ZQ
RZQ
ODT
CKE
CK, CK#
RAS#
WE#
CAS#
CS#
RESET#
CK, CK#
DLL
DQ[15:0]
(1 . . . 16)
(1 . . . 4)
(1, 2)
sw1
sw2
VDDQ/2
BC4
sw1
sw2
VDDQ/2
RTT,nom
RTT(WR)
sw1
sw2
Column 2
(select upper or
lower nibble for BC4)
Data
interface
WRITE
drivers
and
input
logic
ODT
control
VSSQ A12
OTF
VDDQ/2
RTT,nom
RTT(WR)
RTT,nom
2Gb: x4, x8, x16 DDR3 SDRAM
Functional Block Diagrams
PDF: 09005aef826aaadc
2Gb_DDR3_SDRAM.pdf – Rev. K 04/10 EN
15
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