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| 型号： | MT41J128M16HA-107:D |
| 元件分类： | DRAM |
| 英文描述： | 128M X 16 DDR DRAM, PBGA96 |
| 封装： | 9 X 14 MM, LEAD FREE, FBGA-96 |
| 文件页数： | 200/210页 |
| 文件大小： | 12448K |
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Figure 51: MRS to nonMRS Command Timing (tMOD) .................................................................................. 133
Figure 52: Mode Register 0 (MR0) Definitions ................................................................................................ 134
Figure 53: READ Latency .............................................................................................................................. 136
Figure 54: Mode Register 1 (MR1) Definition ................................................................................................. 137
Figure 55: READ Latency (AL = 5, CL = 6) ....................................................................................................... 140
Figure 56: Mode Register 2 (MR2) Definition ................................................................................................. 141
Figure 57: CAS Write Latency ........................................................................................................................ 142
Figure 58: Mode Register 3 (MR3) Definition ................................................................................................. 144
Figure 59: Multipurpose Register (MPR) Block Diagram ................................................................................. 145
Figure 60: MPR System Read Calibration with BL8: Fixed Burst Order Single Readout ..................................... 147
Figure 61: MPR System Read Calibration with BL8: Fixed Burst Order, Back-to-Back Readout ......................... 148
Figure 62: MPR System Read Calibration with BC4: Lower Nibble, Then Upper Nibble ................................... 149
Figure 63: MPR System Read Calibration with BC4: Upper Nibble, Then Lower Nibble ................................... 150
Figure 64: ZQ Calibration Timing (ZQCL and ZQCS) ...................................................................................... 152
Figure 65: Example: Meeting tRRD (MIN) and tRCD (MIN) ............................................................................. 153
Figure 66: Example: tFAW ............................................................................................................................. 154
Figure 67: READ Latency .............................................................................................................................. 155
Figure 68: Consecutive READ Bursts (BL8) .................................................................................................... 157
Figure 69: Consecutive READ Bursts (BC4) .................................................................................................... 157
Figure 70: Nonconsecutive READ Bursts ....................................................................................................... 158
Figure 71: READ (BL8) to WRITE (BL8) .......................................................................................................... 158
Figure 72: READ (BC4) to WRITE (BC4) OTF .................................................................................................. 159
Figure 73: READ to PRECHARGE (BL8) ......................................................................................................... 159
Figure 74: READ to PRECHARGE (BC4) ......................................................................................................... 160
Figure 75: READ to PRECHARGE (AL = 5, CL = 6) ........................................................................................... 160
Figure 76: READ with Auto Precharge (AL = 4, CL = 6) .................................................................................... 160
Figure 77: Data Output Timing – tDQSQ and Data Valid Window ................................................................... 162
Figure 78: Data Strobe Timing – READs ......................................................................................................... 163
Figure 79: Method for Calculating tLZ and tHZ .............................................................................................. 164
Figure 80: tRPRE Timing ............................................................................................................................... 164
Figure 81: tRPST Timing ............................................................................................................................... 165
Figure 82: tWPRE Timing .............................................................................................................................. 167
Figure 83: tWPST Timing .............................................................................................................................. 167
Figure 84: WRITE Burst ................................................................................................................................ 168
Figure 85: Consecutive WRITE (BL8) to WRITE (BL8) ..................................................................................... 169
Figure 86: Consecutive WRITE (BC4) to WRITE (BC4) via MRS or OTF ............................................................ 169
Figure 87: Nonconsecutive WRITE to WRITE ................................................................................................. 170
Figure 88: WRITE (BL8) to READ (BL8) .......................................................................................................... 170
Figure 89: WRITE to READ (BC4 Mode Register Setting) ................................................................................. 171
Figure 90: WRITE (BC4 OTF) to READ (BC4 OTF) ........................................................................................... 172
Figure 91: WRITE (BL8) to PRECHARGE ........................................................................................................ 173
Figure 92: WRITE (BC4 Mode Register Setting) to PRECHARGE ...................................................................... 173
Figure 93: WRITE (BC4 OTF) to PRECHARGE ................................................................................................ 174
Figure 94: Data Input Timing ........................................................................................................................ 175
Figure 95: Self Refresh Entry/Exit Timing ...................................................................................................... 177
Figure 96: Active Power-Down Entry and Exit ................................................................................................ 181
Figure 97: Precharge Power-Down (Fast-Exit Mode) Entry and Exit ................................................................ 182
Figure 98: Precharge Power-Down (Slow-Exit Mode) Entry and Exit ............................................................... 182
Figure 99: Power-Down Entry After READ or READ with Auto Precharge (RDAP) ............................................ 183
Figure 100: Power-Down Entry After WRITE .................................................................................................. 183
Figure 101: Power-Down Entry After WRITE with Auto Precharge (WRAP) ...................................................... 184
Figure 102: REFRESH to Power-Down Entry .................................................................................................. 184
2Gb: x4, x8, x16 DDR3 SDRAM
PDF: 09005aef826aaadc
2Gb_DDR3_SDRAM.pdf – Rev. K 04/10 EN
9
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2006 Micron Technology, Inc. All rights reserved.
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