![](http://datasheet.mmic.net.cn/200000/MT41J128M16HA-107-D_datasheet_15084792/MT41J128M16HA-107-D_52.png)
Table 28: Differential Input Operating Conditions (CK, CK# and DQS, DQS#)
Parameter/Condition
Symbol
Min
Max
Units
Notes
Differential input voltage logic high - slew
VIH,diff(AC)SLEW
+200
n/a
mV
Differential input voltage logic low - slew
VIL,diff(AC)SLEW
n/a
–200
mV
Differential input voltage logic high
VIH,diff(AC)
2 × (VIH(AC) - VREF)
VDD/VDDQ
mV
Differential input voltage logic low
VIL,diff(AC)
VSS/VSSQ
2 × (VREF - VIL(AC))
mV
Differential input crossing voltage relative
to VDD/2 for DQS, DQS#; CK, CK#
VIX
VREF(DC) - 150
VREF(DC) + 150
mV
Differential input crossing voltage relative
to VDD/2 for CK, CK#
VIX (175)
VREF(DC) - 175
VREF(DC) + 175
mV
Single-ended high level for strobes
VSEH
VDDQ/2 + 175
VDDQ
mV
Single-ended high level for CK, CK#
VDD/2 + 175
VDD
mV
Single-ended low level for strobes
VSEL
VSSQ
VDDQ/2 - 175
mV
Single-ended low level for CK, CK#
VSS
VDD/2 - 175
mV
Notes: 1. Clock is referenced to VDD and VSS. Data strobe is referenced to VDDQ and VSSQ.
2. Reference is VREFCA(DC) for clock and for VREFDQ(DC) for strobe.
3. Differential input slew rate = 2 V/ns
4. Defines slew rate reference points, relative to input crossing voltages.
5. Maximum limit is relative to single-ended signals; overshoot specifications are applicable.
6. Minimum limit is relative to single-ended signals; undershoot specifications are applicable.
7. The typical value of VIX(AC) is expected to be about 0.5 × VDD of the transmitting device,
and VIX(AC) is expected to track variations in VDD. VIX(AC) indicates the voltage at which
differential input signals must cross.
8. The VIX extended range (±175mV) is allowed only for the clock; this VIX extended range
is only allowed when the following conditions are met: The single-ended input signals
are monotonic, have the single-ended swing VSEL, VSEH of at least VDD/2 ±250mV, and
the differential slew rate of CK, CK# is greater than 3 V/ns.
9. VIX must provide 25mV (single-ended) of the voltages separation.
Figure 17: VIX for Differential Signals
CK, DQS
VDD/2, VDDQ/2
VIX
CK#, DQS#
VDD, VDDQ
CK, DQS
VDD, VDDQ
VSS, VSSQ
CK#, DQS#
VSS, VSSQ
X
VIX
2Gb: x4, x8, x16 DDR3 SDRAM
Electrical Specifications – DC and AC
PDF: 09005aef826aaadc
2Gb_DDR3_SDRAM.pdf – Rev. K 04/10 EN
52
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2006 Micron Technology, Inc. All rights reserved.